1. Field of the Invention
The present invention relates to a semiconductor memory device such as, for example, a flash EEPROM (Electronically Erasable and Programmable Read Only Memory) capable of holding data even while no voltage is supplied, and especially to a semiconductor memory device including a multiple bit/cell-type memory cell capable of storing a plurality of pieces of data in one bit such as, for example, an MNOS (Metal Nitride Oxide Semiconductor) memory cell.
2. Description of the Background Art
Semiconductor memory devices having elements integrated on a semiconductor substrate for storing data are roughly classified into volatile semiconductor memory devices capable of holding data only while a voltage is supplied and a nonvolatile semiconductor memory devices capable of holding data even while no voltage is supplied. The semiconductor devices in each category are further classified by systems or uses.
One of the systems used most widely today for the latter category of semiconductor memory devices is a flash EEPROM which is electrically writable and erasable. A type of flash EEPROM which is mainstream today uses a floating memory cell including a MOS (Metal Oxide Semiconductor) transistor and a floating gate provided on a channel of the MOS transistor and insulated by an oxide film or the like. A floating memory cell stores data as follows. When electrons are injected to, or removed from, the floating gate, an electric current starts or stops flowing between the source and the drain of the MOS transistor, and thus the gate voltage threshold (hereinafter, represented as “Vt”) is changed.
Recently, MNOS memory cells are again becoming a center of attention. Unlike the floating memory cell, an MNOS memory cell includes an ONO film provided on the channel of the MOS transistor. Vt is changed by injecting electrons or holes into traps in the interface with the ONO film. An MNOS memory cell has a feature that the trapped static charge (electrons or holes) cannot move almost at all. Owing to this feature of the NMOS memory cell, the stored static charge is not all removed even when the oxide film has a defect, unlike in the floating memory cell. Such a feature of the MNOS memory cell is advantageous to solve the problem that data is lost as time passes (retention problem), which is serious today as the oxide film is becoming increasingly thinner.
Also in the MNOS memory cell, the injected static charge can locally stay on the channel because the static charge does not move. In general, the static charge is injected in the vicinity of the drain where hot electrons are generated. Therefore, in the MNOS memory cell, the static charge locally stays on the interface with the ONO film in the vicinity of the drain. Since which side of the NMOS memory cell is the source and which side is the drain is determined by bias conditions, the source and the drain can be exchanged to each other while the semiconductor memory device is being used. Therefore, two areas where the charges locally stay can be formed respectively on two sides of the channel of the MNOS memory cell. By assigning one piece of data to each of these two areas, one MNOS memory cell can store two pieces of data. For these features, expectations for the MNOS memory cells are now increasing.
FIG. 13A is a cross-portional view of a general MNOS memory cell. As shown in FIG. 13A, a LOCOS 101 for device separation, an ONO film 102 and a gate 103 are formed on a semiconductor substrate Sub, and a diffusion layer 104 and a diffusion layer 105 are formed below the LOCOS 101. The gate 103 is generally formed of polysilicon, and is used as a part of a word line in a memory array. The diffusion layer 104 and the diffusion layer 105 act as a drain or a source of the memory cell, and act as a part of buried bit lines in the memory array. Local charge portions 106 and 107 are provided for locally storing charges.
FIG. 13B is a simplified view of the MNOS memory cell shown in FIG. 13A. In FIG. 13B, reference numerals identical to those in FIG. 13A represent elements identical to the elements described above with reference to FIG. 13A. In all the figures attached to this specification, the gate 103, the diffusion layers 104 and 105 (one acts as a drain and the other acts as a source), and the local charge portions 106 and 107 are represented with the reference numerals shown in FIG. 13B.
FIG. 14 is a schematic view of a memory array including conventional memory cells and a peripheral area thereof. FIG. 14 shows a part of the memory array, but an actual array generally includes a great number of memory cells arranged in a direction of rows and a direction of columns. As shown in FIG. 14, a plurality of memory cells M01 through M06 are arranged in an array in the width direction of FIG. 14. Agate of each memory cell is connected to a word line WL0 extending in the width direction and the acting as a common node. Namely, a control gate of the memory cells M01 through M06 is connected to the word line WL0. A source or a drain of each memory cell is connected to one of bit lines BL0 through BL6 extending in the direction perpendicular to the width direction and acting as common nodes. For example, one of the drain and the source of the memory cell M01 is connected to one of the bit lines BL0 and BL1, and the other of the drain and the source of the memory cell M01 is connected to the other of the bit lines BL0 and BL1. Similarly, one of the drain and the source of the memory cell M02 is connected to one of the bit lines BL1 and BL2, and the other of the drain and the source of the memory cell M02 is connected to the other of the bit lines BL1 and BL2.
Each bit line can be selectively connected to one of two inputs of a sense amplifier 209 by a switch 208. The other input of the sense amplifier 209 is connected to a drain of a reference cell R01 via a reference bit line RBL. Used as the reference cell R01 is a CMOS transistor designed such that a current in a middle state between a data state 1 of the memory cell and a data state 0 of the memory cell flows therein. The reference cell R01 is connected to a source line RSL and a word line RWL. A gate of the reference cell R01 is connected to the word line RWL. One of two sides of the reference cell R01, which is not connected to the sense amplifier 209, is a source and is connected to the reference source line RSL.
The conventional memory array shown in FIG. 14 reads data as follows. The current in each of the memory cells M01 through M06 is compared with the current in the reference memory cell R01 to determine the state of the data stored in each memory cell depending on which current is of a higher level. The memory cell, from which the data is to be read, is selected by switching the bit line connected to the sense amplifier 209. The bit line should be selected with care such that the data in the intended one of the two local charge portions 106 and 107 is read without fail.
For example, in order to read a static charge stored in the right local charge portion 107 of the memory cell M02, the bit line BL1 is connected to the sense amplifier 209 and the bit line BL2 is connected to the ground. In order to read a static charge stored in the left local charge portion 106 of the memory cell M02, the bit line BL2 is connected to the sense amplifier 209 and the bit line BL1 is connected to the ground. The bit line connected to the sense amplifier 209 is precharged to a high level immediately before the read. Namely, the direction of the bias voltage of the bit line connected to the memory cell is inverted, and thus the source and the drain are exchanged to switch the local charge portion from which the data is to be read.
Japanese Laid-Open Patent Publication No. 2002-237191 proposes a nonvolatile memory circuit including two floating memory cells for storing a pair of complementary charges. The nonvolatile memory circuit in this publication is described as being capable of reading data at a high speed and with certainty because data is stored as a pair of complementary charges owing to the two memory cells.
In the case of the conventional memory array shown in FIG. 14, the potential of the bit line needs to be high or the current in the reference cell needs to be in the exact middle state between the two data states, in order to have a reading current of a sufficient level for the sense amplifier 209 to determine the state of the data. The former technique is disadvantageous to improving the performance of a semiconductor memory device at a low supply voltage or low power. Specifically, in order to operate a semiconductor memory device at a low supply voltage, the voltage of the bit line needs to be increased using a charge pump, which increases a chip area. The latter technique requires a high precision for the reference cell and a peripheral circuit thereof. This makes the memory cell difficult to design or process-control, and lowers the production yield of the memory cell. In the case of the conventional memory array shown in FIG. 14, the above-mentioned difficulty in obtaining a margin for the reading current means that it is difficult to increase the speed of the reading operation.
The nonvolatile memory circuit described in Japanese Laid-Open Patent Publication No. 2002-237191 requires simply twice the number of memory cells in order to hold one piece of data. This inevitably increases the chip area and lowers the yield.